The present invention relates to a data processor and particularly to a floating point processor useful in high speed array processing.
In performing lengthy computations such as fast Fourier transforms, convolutions and the like, excessive time and expense in computer operation may be involved because of the large number of repetitive calculations which must be sequentially performed. Computer apparatus is known for performing a number of computations substantially in parallel, for example as set forth in U.S. Pat. No. 3,771,141 granted to Glen J. Culler on Nov. 6, 1973. However, circuitry of this type has proved somewhat difficult to manufacture because of the multiplicity of input connections associated with processor registers, rendering difficult the execution thereof on a plurality of conventional circuit boards. Moreover, a processor of this type requires an overriding operation code to define a set of instructions wherein many instructions cannot be utilized simultaneously. Moreover, advantageous computation in floating point arithmetic requires a relatively lengthy software procedure, decreasing the overall speed of the processor.